Conventional PRAMs are memory devices using characteristics of a phase-change material, such as chalcogenide, the electric resistance of which varies according to its crystalline phase. A phase-change material layer formed of chalcogenide is partially changed to be in a crystalline or amorphous phase according to the applied current profile. The crystalline phase of a phase-change material layer can be selectively changed by, for example, temperature variation. That is, a temperature variation occurs by adjusting the current profile, which is applied to the phase-change material layer, thus causing a change in the crystalline phase of the phase-change material layer. For example, a phase-change material layer is heated to its melting point, i.e., about 610° C., by applying a relatively high current pulse for a short duration of time. The phase-change material layer is then rapidly cooled. Thus, the phase-change material layer is changed to be in a highly resistive amorphous phase, i.e., a RESET phase. Inversely, if the phase-change material layer is cooled by applying a relatively low current pulse, it is changed to be in a low resistive crystalline phase, i.e., a SET phase.
Reducing the amount of current required by a phase-change material layer to change its crystalline phase may decrease power dissipation and improve reliability during operation of phase-change memory devices. As a result, attempts have been made to scale down the contact area between the phase-change material layer and a contact plug in order to enhance heating efficiency.
Typically, a conventional phase-change memory device has a vertical contact structure, in which a lower electrode, a phase-change material layer, and an upper electrode are vertically and sequentially connected (see e.g., “OUM-A 180 nm Nonvolatile Memory Cell Element Technology For Stand Alone and Embedded Applications,” by Stefan Lai & Tyler Lowrey, IEDM Tech. Dig. 2001). In this structure, the contact area between the phase-change material layer and the lower electrode is reduced as much as possible so that the current density of the two contact surfaces is rapidly increased, thus causing Joule heating. Here, to reduce the current amount, which will be supplied to a transistor, and enhance Joule heating efficiency, the current density should be increased during programming by reducing the contact area between the phase-change material layer and the lower electrode to be as small as possible. Also, if a lower electrode with a relatively small area is formed, area variations among memories, chips, and wafers should be as small as possible. However, area variations within a permitted range, typically, cannot be easily obtained because of current photolithographic and etching restrictions. Further, a conventional phase-change memory device with a vertical contact structure includes an upper electrode, which is formed on a phase-change material layer using an etching process. Accordingly, the two contact surfaces, i.e., one contact surface between the phase-change material layer and a lower electrode and the other contact surface between the phase-change material layer and the upper electrode, typically cannot be used as phase-change portions. Also, drive conditions of the memory device can depend greatly on contact resistances of the phase-change material layer and a lower electrode. However, since the contact area between the phase-change material layer and the lower electrode is small, the contact resistances may vary within a large range, thus degrading reliability.